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X24C45 1 serial autostore? novram ? xicor, inc. 1991, 1995, 1996 patents pending characteristics subject to change without notice 3833-1.5 2/24/99 t3/c3/d0 ns description the xicor X24C45 is a serial 256 bit novram featuring a static ram configured 16 x 16, overlaid bit-by-bit with a nonvolatile e 2 prom array. the X24C45 is fabricated with xicors advanced cmos floating gate technology. the xicor novram design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. a store opera- tion (ram data to e 2 prom) is completed in 5ms or less and a recall operation (e 2 prom data to ram) is com- pleted in 2s or less. the X24C45 also includes the autostore feature, a user selectable feature that automatically performs a store operation when v cc falls below a preset threshold. xicor novrams are designed for unlimited write opera- tions to ram, either from the host or recalls from e 2 prom and a minimum 1,000,000 store operations. inherent data retention is specified to be greater than 100 years. features ? autostore? novram automatically performs a store operation upon loss of v cc ? single 5 volt supply ? ideal for use with single chip microcomputers minimum i/o interface serial port compatible (cops?, 8051) easily interfaced to microcontroller ports ? software and hardware control of nonvolatile functions ? auto recall on power-up ? ttl and cmos compatible ? low power dissipation active current: 10ma standby current: 50a ? 8-lead pdip and 8-lead soic packages ? high reliability store cycles: 1,000,000 data retention: 100 years 256 bit X24C45 16 x 16 bit 3833 fhd f01 functional diagram nonvolatile e 2 prom control logic column decode row decode 4-bit counter instruction decode instruction register ce (1) di (3) sk (2) do (4) recall (6) as (7) static ram 256-bit recall store autostore? novram is a trademark of xicor, inc. cops is a trademark of national semiconductor corp. a pplication n otes available an3 ? an7 ? an8 ? an15 ? an16 ? an25 ? an29 ? an30 ? an35 ? an36 ? an39 ? an56 ? an69
2 X24C45 pin configuration pin descriptions chip enable (ce) the chip enable input must be high to enable all read/ write operations. ce must remain high following a read or write command until the data transfer is com- plete. ce low places the X24C45 in the low power standby mode and resets the instruction register. there- fore, ce must be brought low after the completion of an operation in order to reset the instruction register in preparation for the next command. serial clock (sk) the serial clock input is used to clock all data into and out of the device. data in (di) data in is the serial data input. data out (do) data out is the serial data output. it is in the high impedance state except during data output cycles in response to a read instruction. autostore output ( as ) as is an open drain output which, when asserted indi- cates v cc has fallen below the autostore threshold (v asth ). as may be wire-ored with multiple open drain outputs and used as an interrupt input to a microcontroller or as an input to a low power reset circuit. recall recall low will initiate an internal transfer of data from e 2 prom to the ram array. pin names symbol description ce chip enable sk serial clock di serial data in do serial data out recall recall input as autostore output v cc +5v v ss ground 3833 pgm t01 3833 fhd f02.1 ce sk di do 1 2 3 4 8 7 6 5 v cc as recall v ss X24C45 dip/soic
X24C45 3 device operation the X24C45 contains an 8-bit instruction register. it is accessed via the di input, with data being clocked in on the rising edge of sk. ce must be high during the entire data transfer operation. table 1. contains a list of the instructions and their operation codes. the most significant bit (msb) of all instructions is a logic one (high), bits 6 through 3 are either ram address bits (a) or dont cares (x) and bits 2 through 0 are the operation codes. the X24C45 requires the instruction to be shifted in with the msb first. after ce is high, the X24C45 will not begin to interpret the data stream until a logic 1 has been shifted in on di. therefore, ce may be brought high with sk running and di low. di must then go high to indicate the start condition of an instruction before the X24C45 will begin any action. in addition, the sk clock is totally static. the user can completely stop the clock and data shifting will be stopped. restarting the clock will resume shifting of data. rcl and recall either a software rcl instruction or a low on the recall input will initiate a transfer of e 2 prom data into ram. this software or hardware recall operation sets an internal previous recall latch. this latch is reset upon power-up and must be intentionally set by the user to enable any write or store operations. although a recall operation is performed upon power-up, the previous recall latch is not set by this operation. wrds and wren internally the X24C45 contains a write enable latch. this latch must be set for either writes to the ram or store operations to the e 2 prom. the wren instruction sets the latch and the wrds instruction resets the latch, disabling both ram writes and e 2 prom stores, effec- tively protecting the nonvolatile data from corruption. the write enable latch is automatically reset on power-up. sto the software sto instruction will initiate a transfer of data from ram to e 2 prom. in order to safeguard against unwanted store operations, the following condi- tions must be true: ? sto instruction issued. ? the internal write enable latch must be set (wren instruction issued). ? the previous recall latch must be set (either a software or hardware recall operation). once the store cycle is initiated, all other device func- tions are inhibited. upon completion of the store cycle, the write enable latch is reset. refer to figure 4 for a state diagram description of enabling/disabling condi- tions for store operations. table 1. instruction set instruction format, i 2 i 1 i 0 operation wrds (figure 3) 1xxxx000 reset write enable latch (disables writes and stores) sto (figure 3) 1xxxx001 store ram data in e 2 prom enas 1xxxx010 enable autostore feature write (figure 2) 1aaaa011 write data into ram address aaaa wren (figure 3) 1xxxx100 set write enable latch (enables writes and stores) rcl (figure 3) 1xxxx101 recall e 2 prom data into ram read (figure 1) 1aaaa11x read data from ram address aaaa 3833 pgm t11 x = dont care a = address
4 X24C45 write the write instruction contains the 4-bit address of the word to be written. the write instruction is immediately followed by the 16-bit word to be written. ce must remain high during the entire operation. ce must go low before the next rising edge of sk. if ce is brought low prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to ram. if ce is kept high for more than 24 sk clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten. read the read instruction contains the 4-bit address of the word to be accessed. unlike the other six instructions, i 0 of the instruction word is a dont care. this provides two advantages. in a design that ties both di and do together, the absence of an eighth bit in the instruction allows the host time to convert an i/o line from an output to an input. secondly, it allows for valid data output during the ninth sk clock cycle. d0, the first bit output during a read operation, is trun- cated. that is, it is internally clocked by the falling edge of the eighth sk clock; whereas, all succeeding bits are clocked by the rising edge of sk (refer to read cycle diagram). low power mode when ce is low, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption. autostore feature the autostore instruction (enas) sets the autostore enable latch, allowing the X24C45 to automatically perform a store operation when v cc falls below the autostore threshold (v asth ). write protection the X24C45 provides two software write protection mechanisms to prevent inadvertent stores of unknown data. power-up condition upon power-up the write enable and autostore enable latches are in the reset state, disabling any store operation. unknown data store the previous recall latch must be set after power-up. it may be set only by performing a software or hardware recall operation, which assures that data in all ram locations is valid. system considerations power-up recall the X24C45 performs a power-up recall that transfers the e 2 prom contents to the ram array. although the data may be read from the ram array, this recall does not set the previous recall latch. during this power-up recall operation, all commands are ignored. therefore, the host should delay any operations with the X24C45 a minimum of t pur after v cc is stable.
X24C45 5 figure 1. ram read 3833 fhd f09.1 figure 2. ram write 3833 fhd f10.1 figure 3. non-data operations 3833 fhd f11.1 1 ce 2345678 1a 1 aaa 1x* sk di 9 101112222324 d 1 d 2 d 3 d 14 d 15 d 0 d 13 do high z *bit 8 of read instructions is dont care d 0 1 ce 2345678 1a 1 aaa 1 sk di 9 101121222324 d 0 d 1 d 2 d 12 d 13 d 14 d 15 0 1 ce 2345678 1x i 2 xxx i 1 i 0 sk di
6 X24C45 figure 4. X24C45 state diagram power on store enabled ram read or write ram read enabled ram read enabled ram read & write enabled wren command ram read ram read power-up recall rcl command or recall sto or wrds cmd ram read & write enabled store enabled autostore enabled ram read or write enas command wren command sto or wrds cmd power off autostore power down 3833 fhd f12.1
X24C45 7 absolute maximum ratings* temperature under bias .................. C65c to +135c storage temperature ....................... C65c to +150c voltage on any pin with respect to v ss ....................................... C1v to +7v d.c. output current ............................................. 5ma lead temperature (soldering, 10 seconds) .............................. 300c *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0c +70c industrial C40c +85c military C55c +125c 3833 pgm t02.1 supply voltage limits X24C45 5v 10% 3833 pgm t03.1 notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. capacitance t a = +25c, f = 1mhz, v cc = 5v symbol parameter max. units test conditions c out (2) output capacitance 8 pf v out = 0v c in (2) input capacitance 6 pf v in = 0v 3833 pgm t06.1 endurance and data retention parameter min. units endurance 100,000 data changes per bit store cycles 1,000,000 store cycles data retention 100 years 3833 pgm t05 d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions l cc1 v cc supply current 10 ma sk = 0.4v/2.4v levels @ 1mhz, (ttl inputs) do = open, all other inputs = v ih i cc2 v cc supply current 2 ma all inputs = v ih , ce = v il (during autostore) do = open, v cc = 4.3v i sb1 v cc standby current 1 ma do = open, ce = v il , (ttl inputs) all other inputs = v ih i sb2 v cc standby current 50 a do = open, ce = v ss (cmos inputs) all other inputs = v cc C 0.3v i li input load current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ll (1) input low voltage C1 0.8 v v ih (1) input high voltage 2 v cc + 1 v v ol output low voltage 0.4 v i ol = 4.2ma v oh output high voltage 2.4 v i oh = C2ma v ol(as) output low voltage (as) 0.4 v i ol (as) = 1ma 3833 pgm t04.3
8 X24C45 a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v 3833 pgm t07.1 equivalent a.c. load circuit a.c. characteristics (over the recommended operating conditions unless otherwise specified.) power-up timing symbol parameter max. units t pur (4) power-up to read operation 200 s t puw (4) power-up to write or store operation 5 ms 3833 pgm t09 notes: (3) sk rise and fall times must be less than 50ns. (4) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are periodically sampled and not 100% tested. 3833 fhd f03 5v 919 w 497 w output 100pf read and write cycle limits symbol parameter min. max. units f sk (3) sk frequency 1 mhz t skh sk positive pulse width 400 ns t skl sk negative pulse width 400 ns t ds data setup time 400 ns t dh data hold time 80 ns t pd1 sk to data bit 0 valid 375 ns t pd sk to data valid 375 ns t z chip enable to output high z 1 s t ces chip enable setup 800 ns t ceh chip enable hold 350 ns t cds chip deselect 800 ns 3833 pgm t08.1
X24C45 9 write cycle 3833 fhd f04 read cycle 3833 fhd f05 sk x12n ce di sk cycle # t ces t skh 1/f sk t skl t ceh t cds t dh t ds sk 6789 10 n d0 d1 dn high z high z ce di do dont care sk cycle # 12 i1 t pd1 t pd t z v ih
10 X24C45 nonvolatile operations previous software write enable recall latch operation recall instruction latch state state hardware recall 0 nop (5) xx software recall 1 rcl x x software store 1 sto set set 3833 pgm t10 array recall limits symbol parameter min. max. units t rcc recall cycle time 2 s t rcp recall pulse width (6) 500 ns t rcz recall to output in high z 500 ns 3833 pgm t11 recall timing 3833 fhd f06 notes: (5) nop designates when the X24C45 is not currently executing an instruction. (6) recall rise time must be <10s. (7) typical values are for t a = 25c and nominal supply voltage. t rcc t rcp t rcz high z recall do software store cycle limits symbol parameter min. typ. (7) max. units t st store time after clock 8 of sto command 2 5 ms 3833 pgm t12.1
X24C45 11 autostore cycle limits symbol parameter min. max. units t asto autostore cycle time 5 ms v asth autostore threshold voltage 4.0 4.3 v v asend autostore cycle end voltage 3.5 v 3833 pgm t13.1 autostore cycle timing diagrams 3833 fhd f08 symbol table as t pur t asto t pur 0v v asth v cc 1 2 3 4 5 v cc volts (v) time (ms) v asth v asend autostore cycle in progress t asto store time waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
12 X24C45 packaging information 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.325 (8.25) 0.300 (7.62) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.140 (3.56) 0.130 (3.30) 0.020 (0.51) 0.015 (0.38) 3926 fhd f01 pin 1 seating plane 0.062 (1.57) 0.058 (1.47) 0.255 (6.47) 0.245 (6.22) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p note: all dimensions in inches (in parentheses in millimeters) 0.092 (2.34) dia. nom. half shoulder width on all end pins optional 0.015 (0.38) max.
X24C45 13 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 C 8 x 45 3926 fhd f22.1 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
14 X24C45 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness tor any purpose. xicor, inc. rese rves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. us. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874, 967; 4,883,976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use as critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reaso nably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. ordering information device X24C45 p t -v v cc limits blank = 5v 10% temperature range blank = commercial = 0c to +70c i = industrial = C40c to +85c m = military = C55c to +125c package p = 8-lead plastic dip s = 8-lead soic

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